Systems for transmitting digital signals often use a phase lock loop (PLL) in clocking related functions, such as recovering timing information from a received signal to provide a clock signal for system timing. In a PLL, a frequency synthesizer is used to output a signal having a frequency which is dependent upon an error signal. The error signal represents the difference between the phase of a reference signal which is supplied to the PLL and an output signal.
Frequency synthesizers are known to be susceptible to extraneous conditions, such as temperature variations or input noise. These conditions affect the frequency of their output signals. When a frequency synthesizer is used in a PLL, these conditions manifest themselves as jitter in the phase of the PLL output signal.
The effect of timing error in a digital signal is to reduce the duration in which a zero or one state can be detected in a given time interval. The given time interval is inversely proportional to the transmission rate of the digital signal. As a result, an increase in the transmission rate of the signal decreases the given time interval, subsequently requiring a decrease in the allowable amount of timing error in the signal.
With increasing transmission rates, specifications for maximum allowable timing error in digital signals are becoming increasingly demanding. System clock signals, which are often provided by PLLs, must meet maximum allowable timing error specifications required by the transmission rate of the signals. As these specifications are reduced, the need for clock sources with improved accuracy and controllability arises.